Automatic Retiming of Two-Phase Latch-Based Resilient Circuits
نویسندگان
چکیده
منابع مشابه
Retiming Level-Clocked Circuits for Latch Count Minimization
Retiming is a powerful transformation that can minimize the number of memory elements in a sequential circuit under clock period constraints. Recent research has led to the development of extremely fast algorithms for retiming edge-triggered circuits. However, level-clocked circuits have the potential to operate faster and require less memory elements than edgetriggered circuits. This paper add...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 2019
ISSN: 0278-0070,1937-4151
DOI: 10.1109/tcad.2018.2846631